SLMP Profile Parameters
Generated user-facing reference. Source: capability/slmp_builtin_ethernet_profiles.json / device-ranges/slmp_device_range_rules.json.
Capability schema 1, capability date 2026-07-06, scope slmp-ethernet-port, default strict mode True. Device-range schema 1, device-range date 2026-07-05.
Purpose
Profile parameters document selectable profile IDs, feature decisions, point limits, write policy, and device availability for user manuals and profile-selection tools.
They do not guarantee that every address or configuration-dependent route will work on a particular PLC installation; use live PLC responses for runtime truth.
Profile Summary
| Profile | Display name | Scope | Role | Base profile | Frame | Compat | Word subcmd | Bit subcmd | Ext word | Ext bit | Verified models |
|---|---|---|---|---|---|---|---|---|---|---|---|
| melsec:iq-r | MELSEC iQ-R (built-in) | builtin-ethernet-port | connection | - | 4E | iQ-R | 0002 | 0003 | 0082 | 0083 | R120PCPU(built-in Ethernet) R120PCPU via RJ71EN71 |
| melsec:iq-r:rj71en71 | MELSEC iQ-R (RJ71EN71) | ethernet-unit | connection | melsec:iq-r | 4E | iQ-R | 0002 | 0003 | 0082 | 0083 | R120PCPU via RJ71EN71 |
| melsec:iq-l | MELSEC iQ-L (built-in) | builtin-ethernet-port | connection | - | 4E | iQ-R | 0002 | 0003 | 0082 | 0083 | L16HCPU(built-in Ethernet) |
| melsec:mx-r | MELSEC MX-R (built-in) | builtin-ethernet-port | connection | melsec:iq-r | 4E | iQ-R | 0002 | 0003 | 0082 | 0083 | Unconfirmed |
| melsec:mx-f | MELSEC MX-F (built-in) | builtin-ethernet-port | connection | melsec:iq-r | 4E | iQ-R | 0002 | 0003 | 0082 | 0083 | Unconfirmed |
| melsec:iq-f | MELSEC iQ-F (built-in) | builtin-ethernet-port | connection | - | 3E | Q/L | 0000 | 0001 | 0080 | 0081 | FX5U-32MR/DS(built-in Ethernet) |
| melsec:qcpu | MELSEC-Q (base profile) | base-profile | base | melsec:qnu | 3E | Q/L | 0000 | 0001 | 0080 | 0081 | No built-in Ethernet CPU target (QnU-derived conservative baseline) |
| melsec:qcpu:qj71e71-100 | MELSEC-Q (QJ71E71-100) | ethernet-unit | connection | melsec:qcpu | 4E | Q/L | 0000 | 0001 | 0080 | 0081 | Q12HCPU via QJ71E71-100 |
| melsec:lcpu | MELSEC-L (built-in) | builtin-ethernet-port | connection | - | 3E | Q/L | 0000 | 0001 | 0080 | 0081 | L26CPU-BT(built-in Ethernet) |
| melsec:lcpu:lj71e71-100 | MELSEC-L (LJ71E71-100) | ethernet-unit | connection | melsec:lcpu | 4E | Q/L | 0000 | 0001 | 0080 | 0081 | L02SCPU via LJ71E71-100 |
| melsec:qnu | MELSEC QnU (built-in) | builtin-ethernet-port | connection | - | 3E | Q/L | 0000 | 0001 | 0080 | 0081 | Q26UDEHCPU(built-in Ethernet) |
| melsec:qnu:qj71e71-100 | MELSEC QnU (QJ71E71-100) | ethernet-unit | connection | melsec:qnu | 4E | Q/L | 0000 | 0001 | 0080 | 0081 | Q26UDEHCPU via QJ71E71-100 |
| melsec:qnudv | MELSEC QnUDV (built-in) | builtin-ethernet-port | connection | - | 3E | Q/L | 0000 | 0001 | 0080 | 0081 | Q06UDVCPU(built-in Ethernet) |
| melsec:qnudv:qj71e71-100 | MELSEC QnUDV (QJ71E71-100) | ethernet-unit | connection | melsec:qnudv | 4E | Q/L | 0000 | 0001 | 0080 | 0081 | Q06UDVCPU via QJ71E71-100 |
Device Definitions
| Classification | Symbol | Device name | Type | Notation |
|---|---|---|---|---|
| User device | X | Input | bit | base16 |
| User device | Y | Output | bit | base16 |
| User device | M | Internal relay | bit | base10 |
| User device | B | Link relay | bit | base16 |
| User device | F | Annunciator | bit | base10 |
| User device | SB | Link special relay | bit | base16 |
| Direct access I/O | DX | Direct input | bit | base16 |
| Direct access I/O | DY | Direct output | bit | base16 |
| User device | V | Edge relay | bit | base10 |
| User device | S | Step relay | bit | base10 |
| User device | T | Timer | TS:bit, TC:bit, TN:word | base10 |
| User device | ST | Retentive timer | STS:bit, STC:bit, STN:word | base10 |
| User device | LT | Long timer | LTS:bit, LTC:bit, LTN:dword | base10 |
| User device | LST | Long retentive timer | LSTS:bit, LSTC:bit, LSTN:dword | base10 |
| User device | C | Counter | CS:bit, CC:bit, CN:word | base10 |
| User device | LC | Long counter | LCS:bit, LCC:bit, LCN:dword | base10 |
| User device | D | Data register | word | base10 |
| User device | W | Link register | word | base16 |
| User device | SW | Link special register | word | base16 |
| User device | L | Latch relay | bit | base10 |
| System Device | SM | Special relay | bit | base10 |
| System Device | SD | Special register | word | base10 |
| Link Direct Device | Jn\X | Link input | bit | base16 |
| Link Direct Device | Jn\Y | Link output | bit | base16 |
| Link Direct Device | Jn\B | Link relay | bit | base16 |
| Link Direct Device | Jn\SB | Link special relay | bit | base16 |
| Link Direct Device | Jn\W | Link register | word | base16 |
| Link Direct Device | Jn\SW | Link special register | word | base16 |
| Module access device | Un\G | Module access device | word | base10 |
| CPU buffer memory access device | U3En\G | CPU buffer memory access device | word | base10 |
| CPU buffer memory access device | U3En\HG | CPU buffer memory access device | word | base10 |
| Index register | Z | Index register | word | base10 |
| Index register | LZ | Long index register | dword | base10 |
| File register | R | File register | word | base10 |
| File register | ZR | File register | word | base10 |
| Refresh data register | RD | Refresh data register | word | base10 |
Device Availability Matrix
o means available for the profile. x means unsupported. Availability does not imply a static range upper bound.
DX and DY are public parser families without range catalog rules; they are listed here only for profile availability.
| Device family | melsec:iq-r | melsec:iq-r:rj71en71 | melsec:iq-l | melsec:mx-r | melsec:mx-f | melsec:iq-f | melsec:qcpu | melsec:qcpu:qj71e71-100 | melsec:lcpu | melsec:lcpu:lj71e71-100 | melsec:qnu | melsec:qnu:qj71e71-100 | melsec:qnudv | melsec:qnudv:qj71e71-100 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| X | o | o | o | o | o | o | o | o | o | o | o | o | o | o |
| Y | o | o | o | o | o | o | o | o | o | o | o | o | o | o |
| M | o | o | o | o | o | o | o | o | o | o | o | o | o | o |
| B | o | o | o | o | o | o | o | o | o | o | o | o | o | o |
| SB | o | o | o | o | o | o | o | o | o | o | o | o | o | o |
| DX | o | o | o | o | o | x | o | o | o | o | o | o | o | o |
| DY | o | o | o | o | o | x | o | o | o | o | o | o | o | o |
| F | o | o | o | o | o | o | o | o | o | o | o | o | o | o |
| V | o | o | o | o | o | x | o | o | o | o | o | o | o | o |
| L | o | o | o | o | o | o | o | o | o | o | o | o | o | o |
| S | o | o | o | o | o | o | o | o | o | o | o | o | o | o |
| D | o | o | o | o | o | o | o | o | o | o | o | o | o | o |
| W | o | o | o | o | o | o | o | o | o | o | o | o | o | o |
| SW | o | o | o | o | o | o | o | o | o | o | o | o | o | o |
| R | o | o | o | o | o | o | o | o | o | o | o | o | o | o |
| T | o | o | o | o | o | o | o | o | o | o | o | o | o | o |
| ST | o | o | o | o | o | o | o | o | o | o | o | o | o | o |
| C | o | o | o | o | o | o | o | o | o | o | o | o | o | o |
| LT | o | o | o | o | o | x | x | x | x | x | x | x | x | x |
| LST | o | o | o | o | o | x | x | x | x | x | x | x | x | x |
| LC | o | o | o | o | o | o | x | x | x | x | x | x | x | x |
| Z | o | o | o | o | o | o | o | o | o | o | o | o | o | o |
| LZ | o | o | o | o | o | o | x | x | x | x | x | x | x | x |
| ZR | o | o | o | o | o | x | o | o | o | o | o | o | o | o |
| RD | o | o | o | o | o | x | x | x | x | x | x | x | x | x |
| SM | o | o | o | o | o | o | o | o | o | o | o | o | o | o |
| SD | o | o | o | o | o | o | o | o | o | o | o | o | o | o |
Feature Matrix
Cell format is state/source.
| Feature | melsec:iq-r | melsec:iq-r:rj71en71 | melsec:iq-l | melsec:mx-r | melsec:mx-f | melsec:iq-f | melsec:qcpu | melsec:qcpu:qj71e71-100 | melsec:lcpu | melsec:lcpu:lj71e71-100 | melsec:qnu | melsec:qnu:qj71e71-100 | melsec:qnudv | melsec:qnudv:qj71e71-100 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Type name | supported/live | supported/policy | supported/live | supported/policy | supported/policy | supported/live | blocked/policy | supported/live | blocked/live | supported/live | blocked/live | supported/live | blocked/live | supported/live |
| Direct read/write | supported/live | supported/policy | supported/live | supported/policy | supported/policy | supported/live | supported/policy | supported/live | supported/live | supported/live | supported/live | supported/live | supported/live | supported/live |
| Random read/write | supported/live | supported/policy | supported/live | supported/policy | supported/policy | supported/live | supported/policy | supported/live | supported/live | supported/live | supported/live | supported/live | supported/live | supported/live |
| Block read/write | supported/live | supported/policy | supported/live | supported/policy | supported/policy | supported/live | blocked/policy | supported/live | blocked/live | supported/live | blocked/live | supported/live | blocked/live | supported/live |
| Monitor | supported/live | supported/policy | supported/live | supported/policy | supported/policy | blocked/live | supported/policy | supported/live | supported/live | supported/live | supported/live | supported/live | supported/live | supported/live |
| U\G module access | config-dependent/live | config-dependent/policy | config-dependent/live | config-dependent/policy | config-dependent/policy | config-dependent/live | blocked/policy | config-dependent/live | blocked/live | config-dependent/live | blocked/live | config-dependent/live | blocked/live | config-dependent/live |
| Link direct | config-dependent/live | config-dependent/policy | config-dependent/live | config-dependent/policy | config-dependent/policy | blocked/live | blocked/policy | config-dependent/live | blocked/live | config-dependent/live | blocked/live | config-dependent/live | blocked/live | config-dependent/live |
| HG CPU buffer | supported/live | supported/policy | blocked/spec | blocked/spec | blocked/spec | blocked/spec | blocked/spec | blocked/spec | blocked/spec | blocked/spec | blocked/spec | blocked/spec | blocked/spec | blocked/spec |
| Long-device route | supported/live | supported/policy | supported/live | supported/policy | supported/policy | supported/live | delegated/policy | blocked/live | delegated/live | blocked/live | delegated/live | blocked/live | delegated/live | blocked/live |
| LZ 32-bit route | supported/live | supported/policy | supported/live | supported/policy | supported/policy | supported/live | delegated/policy | blocked/live | delegated/live | blocked/live | delegated/live | blocked/live | delegated/live | blocked/live |
Point Limit Matrix
| Limit | melsec:iq-r | melsec:iq-r:rj71en71 | melsec:iq-l | melsec:mx-r | melsec:mx-f | melsec:iq-f | melsec:qcpu | melsec:qcpu:qj71e71-100 | melsec:lcpu | melsec:lcpu:lj71e71-100 | melsec:qnu | melsec:qnu:qj71e71-100 | melsec:qnudv | melsec:qnudv:qj71e71-100 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Direct word read | max 960, over C051, [live] | max 960, over C051, [inferred] | max 960, over C051, [live] | max 960, over C051, [inferred] | max 960, over C051, [inferred] | max 960, over C052, [live] | max 960, over C051, [inferred] | max 960, over C051, [live] | max 960, over C051, [live] | max 960, over C051, [live] | max 960, over C051, [live] | max 960, over C051, [live] | max 960, over C051, [live] | max 960, over C051, [live] |
| Direct word write | max 960, over C051, [live] | max 960, over C051, [inferred] | max 960, over C051, [live] | max 960, over C051, [inferred] | max 960, over C051, [inferred] | max 960, over C052, [live] | max 960, over C051, [inferred] | max 960, over C051, [live] | max 960, over C051, [live] | max 960, over C051, [live] | max 960, over C051, [live] | max 960, over C051, [live] | max 960, over C051, [live] | max 960, over C051, [live] |
| Direct bit read | max 7168, over C052, [live] | max 7168, over C052, [inferred] | max 7168, over C052, [live] | max 7168, over C052, [inferred] | max 7168, over C052, [inferred] | max 3584, over C051, [live] | max 7168, over C052, [inferred] | max 7168, over C052, [live] | max 7168, over C052, [live] | max 7168, over C052, [live] | max 7168, over C052, [live] | max 7168, over C052, [live] | max 7168, over C052, [live] | max 7168, over C052, [live] |
| Direct bit write | max 7168, over C052, [live] | max 7168, over C052, [inferred] | max 7168, over C052, [live] | max 7168, over C052, [inferred] | max 7168, over C052, [inferred] | max 3584, over C051, [live] | max 7168, over C052, [inferred] | max 7168, over C052, [live] | max 7168, over C052, [live] | max 7168, over C052, [live] | max 7168, over C052, [live] | max 7168, over C052, [live] | max 7168, over C052, [live] | max 7168, over C052, [live] |
| Random word read | max 96, over C054, [live] | max 96, over C054, [inferred] | max 96, over C054, [live] | max 96, over C054, [inferred] | max 96, over C054, [inferred] | max 192, over C054, [live] | max 192, over C054, [inferred] | max 192, over C054, [live] | max 192, over C054, [live] | max 192, over C054, [live] | max 192, over C054, [live] | max 192, over C054, [live] | max 192, over C054, [live] | max 192, over C054, [live] |
| Random word write | max 80, weighted 960, over C054, [live] | max 80, weighted 960, over C054, [inferred] | max 80, weighted 960, over C054, [live] | max 80, weighted 960, over C054, [inferred] | max 80, weighted 960, over C054, [inferred] | max 160, weighted 1920, over C054, [live] | max 160, weighted 1920, over C054, [inferred] | max 160, weighted 1920, over 4080, [live] | max 160, weighted 1920, over C054, [live] | max 160, weighted 1920, over 4080, [live] | max 160, weighted 1920, over C054, [live] | max 160, weighted 1920, over 4080, [live] | max 160, weighted 1920, over C054, [live] | max 160, weighted 1920, over 4080, [live] |
| Random bit write | max 94, over C053, [live] | max 94, over C053, [inferred] | max 94, over C053, [live] | max 94, over C053, [inferred] | max 94, over C053, [inferred] | max 188, over C053, [live] | max 188, over C053, [inferred] | max 188, over C053, [live] | max 188, over C053, [live] | max 188, over C053, [live] | max 188, over C053, [live] | max 188, over C053, [live] | max 188, over C053, [live] | max 188, over C053, [live] |
| Monitor word register | max 96, over C054, [live] | max 96, over C054, [inferred] | max 96, over C054, [live] | max 96, over C054, [inferred] | max 96, over C054, [inferred] | max 192, over C054, [not-adopted] | max 192, over C054, [inferred] | max 192, over C054, [live] | max 192, over C054, [live] | max 192, over C054, [live] | max 192, over C054, [live] | max 192, over C054, [live] | max 192, over C054, [live] | max 192, over C054, [live] |
| Extended random word read | max 96, over C054, [live] | max 96, over C054, [inferred] | max 96, over C054, [live] | max 96, over C054, [inferred] | max 96, over C054, [inferred] | max 96, over C054, [live] | max 185, over 4080, [inferred] | max 185, over 4080, [live] | max 192, over C054, [inferred] | max 192, over C054, [live] | max 192, over C054, [inferred] | max 192, over C054, [live] | max 192, over C054, [inferred] | max 192, over C054, [live] |
| Extended random word write | max 80, weighted 960, over C054, [live] | max 80, weighted 960, over C054, [inferred] | max 80, weighted 960, over C054, [live] | max 80, weighted 960, over C054, [inferred] | max 80, weighted 960, over C054, [inferred] | max 80, weighted 960, over C054, [live] | max 160, weighted 1920, over 4080, [inferred] | max 160, weighted 1920, over 4080, [live] | max 160, weighted 1920, over 4080, [inferred] | max 160, weighted 1920, over 4080, [live] | max 160, weighted 1920, over 4080, [inferred] | max 160, weighted 1920, over 4080, [live] | max 160, weighted 1920, over 4080, [inferred] | max 160, weighted 1920, over 4080, [live] |
| Extended random bit write | max 94, over C053, [live] | max 94, over C053, [inferred] | max 94, over C053, [live] | max 94, over C053, [inferred] | max 94, over C053, [inferred] | max 94, over C053, [live] | max 188, over C053, [inferred] | max 188, over C053, [live] | max 188, over C053, [inferred] | max 188, over C053, [inferred] | max 188, over C053, [inferred] | max 188, over C053, [live] | max 188, over C053, [inferred] | max 188, over C053, [live] |
| Extended monitor word register | max 96, over C054, [live] | max 96, over C054, [inferred] | max 96, over C054, [live] | max 96, over C054, [inferred] | max 96, over C054, [inferred] | max 96, over C054, [not-adopted] | max 192, over C054, [inferred] | max 192, over C054, [live] | max 192, over C054, [inferred] | max 192, over C054, [live] | max 192, over C054, [inferred] | max 192, over C054, [live] | max 192, over C054, [inferred] | max 192, over C054, [live] |
Note: melsec:iq-f uses live-verified over-limit end codes where word overrun returns C052 and bit overrun returns C051.
Write Policy
| Profile | Policy |
|---|---|
| melsec:iq-r | S=read-only |
| melsec:iq-r:rj71en71 | S=read-only |
| melsec:iq-l | S=read-only |
| melsec:mx-r | S=read-only |
| melsec:mx-f | S=read-only |
| melsec:iq-f | S=read-write |
| melsec:qcpu | S=read-only |
| melsec:qcpu:qj71e71-100 | S=read-write |
| melsec:lcpu | S=read-only |
| melsec:lcpu:lj71e71-100 | S=read-write |
| melsec:qnu | S=read-only |
| melsec:qnu:qj71e71-100 | S=read-write |
| melsec:qnudv | S=read-only |
| melsec:qnudv:qj71e71-100 | S=read-write |
Appendix: How To Read Cells
state/source combines the capability decision with the evidence source. For example, config-dependent/live means state=config-dependent and source=live.
State Values
| State | Meaning |
|---|---|
| supported | Adopted as supported for this profile. Send normally. |
| blocked | Not adopted for this profile. In strict mode, fail before transport. |
| config-dependent | Depends on the PLC configuration, such as whether the target unit exists. Do not guard; send and let the PLC respond. |
| unverified | Unverified. In strict mode, guard as blocked; with strict disabled, allow sending. |
| delegated | Delegated to existing runtime mechanisms, such as SD-derived device range lookup and global rules. The profile does not decide or guard this feature. |
Source Values
| Source | Meaning |
|---|---|
| live | Directly verified on live PLC hardware. |
| policy | Adopted by explicit project/user policy; not necessarily live-verified for that exact profile. |
| spec | Derived from the specification or from a structural hardware constraint. |
| inferred | Inferred from another verified profile or an equivalent command group; not directly live-verified. |
| not-adopted | Recorded to keep the profile schema uniform even though the feature is not adopted for normal use. |